1. Field of the Invention
The present invention relates to a method for manufacturing a capacitor used as a stacked capacitor in a memory cell of a dynamic random access memory (DRAM) device.
2. Description of the Related Art
Generally, in a DRAM cell, a stacked capacitor is comprised of a lower electrode layer, an upper electrode layer, and a dielectric layer therebetween. Recently, in order to increase the capacity of the stacked capacitor, various approaches have been known to make the surface of the lower electrode layer uneven.
In a first prior art method for manufacturing a stacked capacitor, a contact hole is perforated in an insulating layer on a silicon substrate. Then, a tungsten silicide layer is buried in the contact hole, and a polycrystalline silicon layer is formed thereon. Then, the polycrystalline silicon layer is etched by a wet etching process using hot phosphoric acid, to make the surface of the polycrystalline silicon layer uneven. Then, the polycrystalline silicon layer and the tungsten silicide layer are patterned to form a lower electrode (see: JP-A-139882). This will be explained later in detail.
In the first prior art manufacturing method, however, since the height of the polycrystalline silicon layer is reduced by etching with hot phosphoric acid, the increase of the capacity of the stacked capacitor is reduced, and also, the capacity of the stacked capacitor fluctuates greatly. Also, in order to avoid disconnection of the polycrystalline silicon layer, the tungsten silicide layer is required. However, since the contact hole coverage characteristics of the tungsten silicide layer is deteriorated as compared with polycrystalline silicon, the device is not adapted to a fine structure where the contact hole is small in radius and large in height.
In a second prior art method for manufacturing a stacked capacitor, a contact hole is perforated in an insulating layer on a silicon substrate. Then, an amorphous silicon layer is buried in the contact hole. Then, a seeding operation is performed upon the amorphous silicon layer, so that polycrystalline silicon is grown in the amorphus silicon layer, and thus, a hemispherical-grain (HSG) polycrystalline silicon layer is formed thereon. Then, the HSG polycrystalline silicon layer and the amorphous silicon layer are patterned to form a lower electrode (see: H. Watanabe et al., "A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256 Mb DRAMs", IEDM 92, pp. 259-262, 1992). This also will be explained later in detail.
In the second prior art method, however, a seeding apparatus with an ultra-high vacuum chamber is required which increases the manufacturing cost. Also, it is necessary to monitor a natural oxide layer on the amorphous silicon layer, which also increases the manufacturing cost.
In a third prior art method for manufacturing a capacitor, a polycrystalline silicon layer and a tungsten silicide layer are formed on a first insulating layer, and a heating operation is performed upon the tungsten silicide layer in an oxygen atmosphere to make the surface of the tungsten silicide layer uneven. The uneven tungsten silicide layer and the polycrystalline silicon layer are patterned to form word lines. Then, a second insulating layer and a lower electrode layer are formed. In this case, the second insulating layer is so thin that the uneven surfaces of the word lines are transferred to the lower electrode layer. Thus, the surface of the lower electrode is made uneven (see: JP-A-4-152668). This also will be explained later in detail.
In the third prior art manufacturing method, however, since the second insulating layer is very thin, it is impossible to flatten the second insulating layer, thus inviting disconnection of the layers over the second insulating layer. Also, when the tungsten silicide layer is oxidized, tungsten may be peeled off from the tungsten silicide layer.